S912XEG384J3VA Datasheet, PDF (274/1324 Pages) Freescale Semiconductor, Inc – MC9S12XEP100 Reference Manual Covers MC9S12XE Family

Chapter 6 Interrupt (S12XINTV2)
NOTE
Care must be taken to ensure that all exception requests remain active until
the system begins execution of the applicable service routine; otherwise, the
exception request may not get processed at all or the result may be a
spurious interrupt request (vector at address (vector base + 0x0010)).
6.4.5 Reset Exception Requests
The XINT module supports three system reset exception request types (for details please refer to the Clock
and Reset Generator module (CRG)):
1. Pin reset, power-on reset, low-voltage reset, or illegal address reset
2. Clock monitor reset request
3. COP watchdog reset request
6.4.6 Exception Priority
The priority (from highest to lowest) and address of all exception vectors issued by the XINT module upon
request by the CPU is shown in Table 6-10. Generally, all non-maskable interrupts have higher priorities
than maskable interrupts. Please note that between the three software interrupts (Unimplemented op-code
trap request, SWI/BGND request, SYS request) there is no real priority defined because they cannot occur
simultaneously (the S12XCPU executes one instruction at a time).
Table 6-10. Exception Vector Map and Priority
Vector Address⁽¹⁾
Source
0xFFFE
Pin reset, power-on reset, low-voltage reset, illegal address reset
0xFFFC
Clock monitor reset
0xFFFA
COP watchdog reset
(Vector base + 0x00F8) Unimplemented op-code trap
(Vector base + 0x00F6) Software interrupt instruction (SWI) or BDM vector request
(Vector base + 0x0012) System call interrupt instruction (SYS)
(Vector base + 0x0018)
(Vector base + 0x0016)
(Vector base + 0x0014)
(reserved for future use)
XGATE Access violation interrupt request⁽²⁾
CPU Access violation interrupt request⁽³⁾
(Vector base + 0x00F4) XIRQ interrupt request
(Vector base + 0x00F2) IRQ interrupt request
(Vector base +
0x00F0–0x001A)
Device specific I bit maskable interrupt sources (priority determined by the associated
configuration registers, in descending order)
(Vector base + 0x0010) Spurious interrupt
1. 16 bits vector address based
2. only implemented if device features both a Memory Protection Unit (MPU) and an XGATE co-processor
3. only implemented if device features a Memory Protection Unit (MPU)
MC9S12XE-Family Reference Manual Rev. 1.25
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