S912XEG384J3VA Datasheet, PDF (112/1324 Pages) Freescale Semiconductor, Inc – MC9S12XEP100 Reference Manual Covers MC9S12XE Family

Chapter 2 Port Integration Module (S12XEPIMV1)
Table 2-10. DDRC Register Field Descriptions
Field
7-0
DDRC
Description
Port C Data Direction—
This register controls the data direction of pins 7 through 0.
The external bus function controls the data direction for the associated pins. In this case the data direction bits will
not change.
When operating a pin as a general purpose I/O, the associated data direction bit determines whether it is an input
or output.
1 Associated pin is configured as output.
0 Associated pin is configured as high-impedance input.
2.3.10 Port D Data Direction Register (DDRD)
Address 0x0007 (PRR)
Access: User read/write⁽¹⁾
7
R
DDRD7
W
6
DDRD6
5
DDRD5
4
DDRD4
3
DDRD3
2
DDRD2
1
DDRD1
0
DDRD0
Reset
0
0
0
0
0
0
0
0
Figure 2-8. Port D Data Direction Register (DDRD)
1. Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other modes the data source
is depending on the data direction value.
Write: Anytime. In emulation modes, write operations will also be directed to the external bus.
Table 2-11. DDRD Register Field Descriptions
Field
7-0
DDRD
Description
Port D Data Direction—
This register controls the data direction of pins 7 through 0.
When used with the external bus this function controls the data direction for the associated pins. In this case the data
direction bits will not change.
When operating a pin as a general purpose I/O, the associated data direction bit determines whether it is an input
or output.
1 Associated pin is configured as output.
0 Associated pin is configured as high-impedance input.
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