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Chapter 10 XGATE (S12XGATEV3)
Table 10-23. Access Detail Notation
V — Vector fetch: always an aligned word read, lasts for at least one RISC core cycle
P — Program word fetch: always an aligned word read, lasts for at least one RISC core cycle
r — 8 bit data read: lasts for at least one RISC core cycle
R — 16 bit data read: lasts for at least one RISC core cycle
w — 8 bit data write: lasts for at least one RISC core cycle
W — 16 bit data write: lasts for at least one RISC core cycle
A — Alignment cycle: no read or write, lasts for zero or one RISC core cycles
f — Free cycle: no read or write, lasts for one RISC core cycles
Special Cases
PP/P — Branch: PP if branch taken, P if not
10.8.4 Thread Execution
When the RISC core is triggered by an interrupt request (see Figure 10-1) it first executes a vector fetch
sequence which performs three bus accesses:
1. A V-cycle to fetch the initial content of the program counter.
2. A V-cycle to fetch the initial content of the data segment pointer (R1).
3. A P-cycle to load the initial opcode.
Afterwards a sequence of instructions (thread) is executed which is terminated by an "RTS" instruction. If
further interrupt requests are pending after a thread has been terminated, a new vector fetch will be
performed. Otherwise the RISC core will either resume a previous thread (beginning with a P-cycle to
refetch the interrupted opcode) or it will become idle until a new interrupt request is received. A thread can
only be interrupted by an interrupt request of higher priority.
10.8.5 Instruction Glossary
This section describes the XGATE instruction set in alphabetical order.
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