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| S912XEG384J3VA Datasheet, PDF (727/1324 Pages) Freescale Semiconductor, Inc – MC9S12XEP100 Reference Manual Covers MC9S12XE Family | |||
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Chapter 20 Serial Communication Interface (S12SCIV5)
20.3.2 Register Descriptions
This section consists of register descriptions in address order. Each description includes a standard register
diagram with an associated ï¬gure number. Writes to a reserved register locations do not have any effect
and reads of these locations return a zero. Details of register bit and ï¬eld function follow the register
diagrams, in bit order.
Register
Name
Bit 7
0x0000
R
SCIBDH1 W IREN
0x0001
R
SCIBDL1 W SBR7
6
TNP1
SBR6
5
TNP0
4
3
2
SBR12
SBR11
SBR10
1
SBR9
SBR5
SBR4
SBR3
SBR2
SBR1
Bit 0
SBR8
SBR0
0x0002
R
SCICR11
LOOPS
W
SCISWAI
RSRC
M
WAKE
ILT
PE
PT
0x0000
R
0
0
0
0
SCIASR12
RXEDGIF
W
BERRV BERRIF
BKDIF
0x0001
R
0
0
0
0
0
SCIACR12
RXEDGIE
W
BERRIE BKDIE
0x0002
R
0
0
0
0
0
SCIACR22 W
BERRM1 BERRM0 BKDFE
0x0003
R
SCICR2 W
TIE
TCIE
RIE
ILIE
TE
0x0004
R TDRE
TC
RDRF
IDLE
OR
SCISR1 W
RE
RWU
SBK
NF
FE
PF
0x0005
R
0
SCISR2
AMAP
W
0
RAF
TXPOL
RXPOL
BRK13
TXDIR
0x0006
R
R8
0
0
0
0
0
0
SCIDRH W
T8
0x0007
R
R7
R6
R5
R4
R3
R2
R1
R0
SCIDRL W
T7
T6
T5
T4
T3
T2
T1
T0
1.These registers are accessible if the AMAP bit in the SCISR2 register is set to zero.
2,These registers are accessible if the AMAP bit in the SCISR2 register is set to one.
= Unimplemented or Reserved
Figure 20-2. SCI Register Summary
MC9S12XE-Family Reference Manual Rev. 1.25
Freescale Semiconductor
727
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