S912XEG384J3VA Datasheet, PDF (255/1324 Pages) Freescale Semiconductor, Inc – MC9S12XEP100 Reference Manual Covers MC9S12XE Family

Chapter 5 External Bus Interface (S12XEBIV4)
internal RAM and misaligned XGATE PRR accesses in emulation modes are the only type of access that
are able to produce LSTRB = ADDR0 = 1. This is summarized in Table 5-20.
Table 5-20. Access in Emulation Modes and Special Test Mode
Access
Word write of data on DATA[15:0] at an even and even+1
address
Byte write of data on DATA[7:0] at an odd address
Byte write of data on DATA[15:8] at an even address
Word write at an odd and odd+1 internal RAM address
(misaligned — only in emulation modes)
Word read of data on DATA[15:0] at an even and even+1
address
Byte read of data on DATA[7:0] at an odd address
Byte read of data on DATA[15:8] at an even address
Word read at an odd and odd+1 internal RAM address
(misaligned - only in emulation modes)
DATA[15:8]
DATA[7:0]
RW LSTRB ADDR0
I/O data(addr) I/O data(addr)
0
0
0 Out data(even) Out data(odd)
0
0
0
1
0
1
1
In
x
Out data(odd)
0 Out data(odd) In
x
1 Out data(odd+1) Out data(odd)
1
0
0
In data(even) In data(even+1)
1
0
1
1
1
1
1
In
x
In data(odd)
0
In data(even) In
x
1
In data(odd+1) In data(odd)
MC9S12XE-Family Reference Manual Rev. 1.25
Freescale Semiconductor
255