S912XEG384J3VA Datasheet, PDF (378/1324 Pages) Freescale Semiconductor, Inc – MC9S12XEP100 Reference Manual Covers MC9S12XE Family

Chapter 10 XGATE (S12XGATEV3)
S12X_CPU
.........
1 ⇒ XGSEM[n]
XGSEM[n] 1?
XGATE
.........
SSEM
BCC?
critical
code
sequence
critical
code
sequence
0 ⇒ XGSEM[n]
CSEM
.........
.........
Figure 10-25. Algorithm for Locking and Releasing Semaphores
10.4.5 Software Error Detection
Upon detecting an error condition caused by erratic application code, the XGATE module will
immediately terminate program execution and trigger a non-maskable interrupt to the S12X_CPU. There
are three error conditions:
• Execution of an illegal opcode
• Illegal opcode fetches
• Illegal load or store accesses
All opcodes which are not listed in section Section 10.8, “Instruction Set” are illegal opcodes. Illegal
opcode fetches as well as illegal load and store accesses are defined on chip level. Refer to the
S12X_MMC Section for a detailed information.
NOTE
When executing a branch (BCC, BCS,...), a jump (JAL) or an RTS
instruction, the XGATE prefetches and discards the opcode of the following
instruction. The XGATE will perform its software error handling actions
(see above) if this opcode fetch is illegal.
MC9S12XE-Family Reference Manual Rev. 1.25
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