S912XEG384J3VA Datasheet, PDF (490/1324 Pages) Freescale Semiconductor, Inc – MC9S12XEP100 Reference Manual Covers MC9S12XE Family

Chapter 11 S12XE Clocks and Reset Generator (S12XECRGV1)
The Sequence for clock quality check is shown in Figure 11-18.
CLOCK OK
CM FAIL
POR
LVR
EXIT FULL STOP
SCME=1 &
FSTWKP=1
?
NO
YES _{NUM = 0}
NO
ENTER SCM
CLOCK MONITOR RESET
FSTWKP = 0
?
YES
NUM = 50
CHECK WINDOW
OSC OK
NO
?
YES
SCM
YES
ACTIVE?
NO
ENTER SCM
YES
NUM = NUM-1
YES
NO
NUM > 0
?
NO
SCM
ACTIVE?
NUM = 0
YES
SCME = 1
NO
?
SWITCH TO OSCCLK
EXIT SCM
Figure 11-18. Sequence for Clock Quality Check
NOTE
Remember that in parallel to additional actions caused by Self Clock Mode
or Clock Monitor Reset¹ handling the clock quality checker continues to
check the OSCCLK signal.
NOTE
The Clock Quality Checker enables the IPLL and the voltage regulator
(VREG) anytime a clock check has to be performed. An ongoing clock
quality check could also cause a running IPLL (f_SCM) and an active VREG
during Pseudo Stop Mode.
1. A Clock Monitor Reset will always set the SCME bit to logical’1’.
MC9S12XE-Family Reference Manual Rev. 1.25
490
Freescale Semiconductor