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S912XEG384J3VA Datasheet, PDF (368/1324 Pages) Freescale Semiconductor, Inc – MC9S12XEP100 Reference Manual Covers MC9S12XE Family
Chapter 10 XGATE (S12XGATEV3)
Table 10-11. XGSWT Field Descriptions
Field
Description
15–8
Software Trigger Mask — These bits control the write access to the XGSWT bits. Each XGSWT bit can only
XGSWTM[7:0] be written if a "1" is written to the corresponding XGSWTM bit in the same access.
Read:
These bits will always read "0".
Write:
0 Disable write access to the XGSWT in the same bus cycle
1 Enable write access to the corresponding XGSWT bit in the same bus cycle
7–0
XGSWT[7:0]
Software Trigger Bits — These bits act as interrupt flags that are able to trigger XGATE software channels.
They can only be set and cleared by software.
Read:
0 No software trigger pending
1 Software trigger pending if the XGIE bit is set
Write:
0 Clear Software Trigger
1 Set Software Trigger
NOTE
The XGATE channel IDs that are associated with the eight software triggers
are determined on chip integration level. (see Section “Interrupts“ of the
device overview)
XGATE software triggers work like any peripheral interrupt. They can be
used as XGATE requests as well as S12X_CPU interrupts. The target of the
software trigger must be selected in the S12X_INT module.
10.3.1.10 XGATE Semaphore Register (XGSEM)
The XGATE provides a set of eight hardware semaphores that can be shared between the S12X_CPU and
the XGATE RISC core. Each semaphore can either be unlocked, locked by the S12X_CPU or locked by
the RISC core. The RISC core is able to lock and unlock a semaphore through its SSEM and CSEM
instructions. The S12X_CPU has access to the semaphores through the XGATE Semaphore Register
(Figure 10-12). Refer to section Section 10.4.4, “Semaphores” for details.
Module Base +0x0001A
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R0
0
0
0
0
0
0
0
W
XGSEMM[7:0]
XGSEM[7:0]
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 10-12. XGATE Semaphore Register (XGSEM)
Read: Anytime
Write: Anytime (see Section 10.4.4, “Semaphores”)
MC9S12XE-Family Reference Manual Rev. 1.25
368
Freescale Semiconductor