S912XEG384J3VA Datasheet, PDF (164/1324 Pages) Freescale Semiconductor, Inc – MC9S12XEP100 Reference Manual Covers MC9S12XE Family

Chapter 2 Port Integration Module (S12XEPIMV1)
2.3.85 Port R Data Register (PTR)
Address 0x0368
7
R
PTR7
W
Altern.
Function ^TIMIOC7
Reset
0
1. Read: Anytime.
Write: Anytime.
6
PTR6
5
PTR5
4
PTR4
3
PTR3
2
PTR2
TIMIOC6 TIMIOC5 TIMIOC4 TIMIOC3 TIMIOC2
0
0
0
0
0
Figure 2-83. Port R Data Register (PTR)
Access: User read/write⁽¹⁾
1
0
PTR1
PTR0
TIMIOC1
0
TIMIOC0
0
Field
7-0
PTR
Table 2-81. PTR Register Field Descriptions
Description
Port R general purpose input/output data—Data Register
Port R pins 7 through 0 are associated with TIM channels TIMIOC7 through TIMIOC0.
When not used with the alternative function, these pins can be used as general purpose I/O.
If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the
buffered pin input state is read.
2.3.86 Port R Input Register (PTIR)
Address 0x0369
7
R PTIR7
6
PTIR6
5
PTIR5
4
PTIR4
3
PTIR3
2
PTIR2
W
Reset
u
u
u
u
u
u
= Unimplemented or Reserved
u = Unaffected by reset
Figure 2-84. Port R Input Register (PTIR)
1. Read: Anytime.
Write:Never, writes to this register have no effect.
Access: User read⁽¹⁾
1
PTIR1
0
PTIR0
u
u
Field
7-0
PTIR
Table 2-82. PTIR Register Field Descriptions
Description
Port R input data—
This register always reads back the buffered state of the associated pins. This can also be used to detect overload
or short circuit conditions on output pins.
MC9S12XE-Family Reference Manual Rev. 1.25
164
Freescale Semiconductor