S912XEG384J3VA Datasheet, PDF (825/1324 Pages) Freescale Semiconductor, Inc – MC9S12XEP100 Reference Manual Covers MC9S12XE Family

Chapter 23 Voltage Regulator (S12VREGL3V3V1)
Table 23-9. Selectable Autonomous Periodical Interrupt Periods (continued)
APICLK
APIR[15:0]
Selected Period
1
FFFF
131072 * bus clock period
1. When trimmed within specified accuracy. See electrical specifications for details.
The period can be calculated as follows depending of APICLK:
Period = 2*(APIR[15:0] + 1) * 0.1 ms or period = 2*(APIR[15:0] + 1) * bus clock period
23.3.2.6 Reserved 06
The Reserved 06 is reserved for test purposes.
0x02F6
7
6
5
4
3
2
1
0
R
0
0
0
0
0
0
0
0
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 23-8. Reserved 06
23.3.2.7 High Temperature Trimming Register (VREGHTTR)
The VREGHTTR register allows to trim the VREG temperature sense.
Fiption
0x02F7
7
6
5
4
3
2
R
0
0
0
HTOEN
HTTR3
HTTR2
W
Reset
0
0
0
0
0¹
0¹
1. Reset value is either 0 or preset by factory. See Section 1 (Device Overview) for details.
= Unimplemented or Reserved
Figure 23-9. VREGHTTR
Table 23-10. VREGHTTR field descriptions
1
HTTR1
0¹
Field
Description
7
HTOEN
High Temperature Offset Enable Bit — If set the temperature sense offset is enabled
0 The temperature sense offset is disabled
1 The temperature sense offset is enabled
3–0
High Temperature Trimming Bits — See Table 23-11 for trimming effects.
HTTR[3:0]
0
HTTR0
0¹
Bit
HTTR[3]
Table 23-11. Trimming Effect
Trimming Effect
Increases V_HT twice of HTTR[2]
MC9S12XE-Family Reference Manual Rev. 1.25
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