S912XEG384J3VA Datasheet, PDF (118/1324 Pages) Freescale Semiconductor, Inc – MC9S12XEP100 Reference Manual Covers MC9S12XE Family

Chapter 2 Port Integration Module (S12XEPIMV1)
The ECLKCTL register is used to control the availability of the free-running clocks and the free-running
clock divider.
Table 2-16. ECLKCTL Register Field Descriptions
Field
Description
7
NECLK
No ECLK—Disable ECLK output
This bit controls the availability of a free-running clock on the ECLK pin.
Clock output is always active in emulation modes and if enabled in all other operating modes.
1 ECLK disabled
0 ECLK enabled
6
NCLKX2
No ECLKX2—Disable ECLKX2 output
This bit controls the availability of a free-running clock on the ECLKX2 pin. This clock has a fixed rate of twice the
internal Bus Clock.
Clock output is always active in emulation modes and if enabled in all other operating modes.
1 ECLKX2 disabled
0 ECLKX2 enabled
5
DIV16
Free-running ECLK predivider—Divide by 16
This bit enables a divide-by-16 stage on the selected EDIV rate.
1 Divider enabled: ECLK rate = EDIV rate divided by 16
0 Divider disabled: ECLK rate = EDIV rate
4-0
EDIV
Free-running ECLK Divider—Configure ECLK rate
These bits determine the rate of the free-running clock on the ECLK pin. Divider is always disabled in emulation
modes and active as programmed in all other operating modes.
00000 ECLK rate = Bus Clock rate
00001 ECLK rate = Bus Clock rate divided by 2
00010 ECLK rate = Bus Clock rate divided by 3, ...
11111 ECLK rate = Bus Clock rate divided by 32
2.3.16 PIM Reserved Register
Address 0x001D (PRR)
7
6
5
4
3
2
R
0
0
0
0
0
0
W
Reset
0
0
0
0
0
0
= Unimplemented or Reserved
1. Read: Always reads 0x00
Write: Unimplemented
Figure 2-14. PIM Reserved Register
Access: User read⁽¹⁾
1
0
0
0
0
0
MC9S12XE-Family Reference Manual Rev. 1.25
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Freescale Semiconductor