S912XEG384J3VA Datasheet, PDF (674/1324 Pages) Freescale Semiconductor, Inc – MC9S12XEP100 Reference Manual Covers MC9S12XE Family

Chapter 17 Periodic Interrupt Timer (S12PIT24B8CV2)
17.5 Initialization
17.5.1 Startup
Set the configuration registers before the PITE bit in the PITCFLMT register is set. Before PITE is set, the
configuration registers can be written in arbitrary order.
17.5.2 Shutdown
When the PITCE register bits, the PITINTE register bits or the PITE bit in the PITCFLMT register are
cleared, the corresponding PIT interrupt flags are cleared. In case of a pending PIT interrupt request, a
spurious interrupt can be generated. Two strategies, which avoid spurious interrupts, are recommended:
1. Reset the PIT interrupt flags only in an ISR. When entering the ISR, the I mask bit in the CCR is
set automatically. The I mask bit must not be cleared before the PIT interrupt flags are cleared.
2. After setting the I mask bit with the SEI instruction, the PIT interrupt flags can be cleared. Then
clear the I mask bit with the CLI instruction to re-enable interrupts.
17.5.3 Flag Clearing
A flag is cleared by writing a one to the flag bit. Always use store or move instructions to write a one in
certain bit positions. Do not use the BSET instructions. Do not use any C-constructs that compile to BSET
instructions. “BSET flag_register, #mask” must not be used for flag clearing because BSET is a read-
modify-write instruction which writes back the “bit-wise or” of the flag_register and the mask into the
flag_register. BSET would clear all flag bits that were set, independent from the mask.
For example, to clear flag bit 0 use: MOVB #$01,PITTF.
17.6 Application Information
To get started quickly with the PIT24B8C module this section provides a small code example how to use
the block. Please note that the example provided is only one specific case out of the possible configurations
and implementations.
Functionality: Generate an PIT interrupt on channel 0 every 500 PIT clock cycles.
ORG
LDS
MOVW
CODESTART
; place the program into specific
; range (to be selected)
RAMEND
; load stack pointer to top of RAM
#CH0_ISR,VEC_PIT_CH0 ; Change value of channel 0 ISR adr
; ******************** Start PIT Initialization *******************************************************
CLR
MOVB
CLR
MOVB
MOVW
PITCFLMT
#$01,PITCE
PITMUX
#$63,PITMTLD0
#$0004,PITLD0
; disable PIT
; enable timer channel 0
; ch0 connected to micro timer 0
; micro time base 0 equals 100 clock cycles
; time base 0 eq. 5 micro time bases 0 =5*100 = 500
MC9S12XE-Family Reference Manual Rev. 1.25
674
Freescale Semiconductor