S912XEG384J3VA Datasheet, PDF (171/1324 Pages) Freescale Semiconductor, Inc – MC9S12XEP100 Reference Manual Covers MC9S12XE Family

Chapter 2 Port Integration Module (S12XEPIMV1)
NOTE
Due to internal synchronization circuits, it can take up to 2 bus clock cycles
until the correct value is read on PTL or PTIL registers, when changing the
DDRL register.
2.3.96 Port L Reduced Drive Register (RDRL)
Address 0x0373
R
W
Reset
7
RDRL7
0
1. Read: Anytime.
Write: Anytime.
6
RDRL6
5
RDRL5
4
RDRL4
3
RDRL3
2
RDRL2
0
0
0
0
0
Figure 2-94. Port L Reduced Drive Register (RDRL)
Access: User read/write⁽¹⁾
1
0
RDRL1
RDRL0
0
0
Table 2-91. RDRL Register Field Descriptions
Field
7-0
RDRL
Description
Port L reduced drive—Select reduced drive for outputs
This register configures the drive strength of output pins 7 through 0 as either full or reduced independent of the
function used on the pins. If a pin is used as input this bit has no effect.
1 Reduced drive selected (approx. 1/5 of the full drive strength).
0 Full drive strength enabled.
2.3.97 Port L Pull Device Enable Register (PERL)
Address 0x0374
R
W
Reset
7
PERL7
1
1. Read: Anytime.
Write: Anytime.
6
PERL6
5
PERL5
4
PERL4
3
PERL3
2
PERL2
Access: User read/write⁽¹⁾
1
0
PERL1
PERL0
1
1
1
1
1
1
1
Figure 2-95. Port L Pull Device Enable Register (PERL)
Table 2-92. PERL Register Field Descriptions
Field
7-0
PERL
Description
Port L pull device enable—Enable pull devices on input pins
These bits configure whether a pull device is activated, if the associated pin is used as an input. This bit has no effect
if the pin is used as an output. Out of reset all pull devices are enabled.
1 Pull device enabled.
0 Pull device disabled.
MC9S12XE-Family Reference Manual Rev. 1.25
Freescale Semiconductor
171