S912XEG384J3VA Datasheet, PDF (247/1324 Pages) Freescale Semiconductor, Inc – MC9S12XEP100 Reference Manual Covers MC9S12XE Family

5.3.2.2
Chapter 5 External Bus Interface (S12XEBIV4)
ASIZ[4:0]
00011
:
10110
10111
:
11111
Table 5-5. External Address Bus Size
Available External Address Lines
ADDR[2:1], UDS
:
ADDR[21:1], UDS
ADDR[22:1], UDS
External Bus Interface Control Register 1 (EBICTL1)
Module Base +0x000F (PRR)
7
6
5
4
3
2
1
R
0
0
EXSTR12 EXSTR11 EXSTR10
EXSTR02 EXSTR01
W
Reset
0
1
1
1
0
1
1
= Unimplemented or Reserved
Figure 5-4. External Bus Interface Control Register 1 (EBICTL1)
0
EXSTR00
1
Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other
modes the data is read from this register.
Write: Anytime. In emulation modes, write operations will also be directed to the external bus.
This register allows programming of two independent values determining the amount of additional stretch
cycles for external accesses (wait states).
With two bits in S12X_MMC register MMCCTL0 for every individual CSx line one of the two counter
options or the EWAIT input is selected as stretch source. The chip select outputs can also be disabled to
free up the pins for alternative functions (Table 5-6). Refer also to S12X_MMC section for register bit
descriptions.
Table 5-6. Chip select function
CSxE1
0
0
1
1
CSxE0
0
1
0
1
Function
CSx disabled
CSx stretched with EXSTR0
CSx stretched with EXSTR1
CSx stretched with EWAIT
If EWAIT input usage is selected in MMCCTL0 the minimum number of stretch cycles is 2 for accesses
to the related address range.
If configured respectively, stretch cycles are added as programmed or dependent on EWAIT in normal
expanded mode and emulation expanded mode; function not available in all other operating modes.
MC9S12XE-Family Reference Manual Rev. 1.25
Freescale Semiconductor
247