S912XEG384J3VA Datasheet, PDF (1202/1324 Pages) Freescale Semiconductor, Inc – MC9S12XEP100 Reference Manual Covers MC9S12XE Family

Appendix A Electrical Characteristics
NOTE
Connecting VDDR to VSS disables the internal voltage regulator.
The VDDF_, VSS1 pin pair supplies the internal NVM logic.
The VDD, VSS2 are the supply pins for the internal digital logic.
VDDPLL, VSSPLL pin pair supply the oscillator and the PLL.
VSS1, VSS2 and VSS3 are internally connected by metal.
VDDA1, and VDDA2 are internally connected by metal.
All VDDX pins are internally connected by metal.
All VSSX pins are internally connected by metal.
VDDA is connected to all VDDX pins by diodes for ESD protection such that VDDX must not exceed
VDDA by more than a diode voltage drop. VDDA can exceed VDDX by more than a diode drop in order
to support applications with a 5V A/D converter range and 3.3V I/O pin range.
VSSA and VSSX are connected by anti-parallel diodes for ESD protection.
NOTE
In the following context V_DD35 is used for either VDDA, VDDR, and
VDDX; V_SS35 is used for either VSSA and VSSX unless otherwise noted.
I_DD35 denotes the sum of the currents flowing into the VDDA and VDDR
pins. The Run mode current in the VDDX domain is external load
dependent.
V_DD is used for VDD, V_SS is used for VSS1, VSS2 and VSS3.
V_DDPLL is used for VDDPLL, V_SSPLL is used for VSSPLL
I_DD is used for the sum of the currents flowing into VDD, VDDF and
VDDPLL.
A.1.3 Pins
There are four groups of functional pins.
A.1.3.1 I/O Pins
Standard I/O pins have a level in the range of 3.13V to 5.5 V. This class of pins is comprised of all port I/O
pins (including PortAD), BKGD and the RESET pins.The internal structure of all those pins is identical;
however, some of the functionality may be disabled. For example the BKGD pin pull up is always enabled.
A.1.3.2 Analog Reference
This group is made up by the V_RH and V_RL pins.
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MC9S12XE-Family Reference Manual Rev. 1.25
Freescale Semiconductor