S912XEG384J3VA Datasheet, PDF (168/1324 Pages) Freescale Semiconductor, Inc – MC9S12XEP100 Reference Manual Covers MC9S12XE Family

Chapter 2 Port Integration Module (S12XEPIMV1)
Table 2-87. PTR Routing Register Field Descriptions (continued)
Field
Description
5
PTRRR
Port R routing—
This register configures the re-routing of the associated TIM channel.
1 TIMIOC5 is available on PP5
0 TIMIOC5 is available on PR5
4
PTRRR
Port R routing—
This register configures the re-routing of the associated TIM channel.
1 TIMIOC4 is available on PP4
0 TIMIOC4 is available on PR4
3
PTRRR
Port R routing—
This register configures the re-routing of the associated TIM channel.
1 TIMIOC3 is available on PP3
0 TIMIOC3 is available on PR3
2
PTRRR
Port R routing—
This register configures the re-routing of the associated TIM channel.
1 TIMIOC2 is available on PP2
0 TIMIOC2 is available on PR2
1
PTRRR
Port R routing—
This register configures the re-routing of the associated TIM channel.
1 TIMIOC1 is available on PP1
0 TIMIOC1 is available on PR1
0
PTRRR
Port R routing—
This register configures the re-routing of the associated TIM channel.
1 TIMIOC0 is available on PP0
0 TIMIOC0 is available on PR0
2.3.93 Port L Data Register (PTL)
Address 0x0370
R
W
Altern.
Function
Reset
7
PTL7
(TXD7)
0
1. Read: Anytime.
Write: Anytime.
6
PTLT6
5
PTL5
4
PTL4
3
PTL3
2
PTL2
(RXD7)
0
(TXD6)
(RXD6)
(TXD5)
(RXD5)
0
0
0
0
Figure 2-91. Port L Data Register (PTL)
Access: User read/write⁽¹⁾
1
0
PTL1
PTL0
(TXD4)
0
(RXD4)
0
MC9S12XE-Family Reference Manual Rev. 1.25
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