S912XEG384J3VA Datasheet, PDF(828/1324 Page) Freescale Semiconductor, Inc – MC9S12XEP100 Reference Manual Covers MC9S12XE Family

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S912XEG384J3VA Datasheet, PDF (828/1324 Pages) Freescale Semiconductor, Inc – MC9S12XEP100 Reference Manual Covers MC9S12XE Family

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Chapter 23 Voltage Regulator (S12VREGL3V3V1)

The API Trimming bits APITR[5:0] must be set so the minimum period equals 0.2 ms if stable frequency

is desired.

See Table 23-7 for the trimming effect of APITR.

NOTE

The ï¬rst period after enabling the counter by APIFE might be reduced by

API start up delay tsdel. The API internal RC oscillator clock is not available

if VREG_3V3 is in Shutdown Mode.

It is possible to generate with the API a waveform at an external pin by enabling the API by setting APIFE

and enabling the external access with setting APIEA. By setting APIES the waveform can be selected. If

APIES is set, then at the external pin a clock is visible with 2 times the selected API Period (Table 23-9).

If APIES is not set, then at the external pin will be a high pulse at the end of every selected period with the

size of half of the min period (Table 23-9). See device level speciï¬cation for connectivity.

23.4.9 Resets

This section describes how VREG_3V3 controls the reset of the MCU.The reset values of registers and

signals are provided in Section 23.3, âMemory Map and Register Deï¬nitionâ. Possible reset sources are

listed in Table 23-12.

Table 23-12. Reset Sources

Reset Source

Power-on reset

Low-voltage reset

Local Enable

Always active

Available only in Full Performance Mode

23.4.10 Description of Reset Operation

23.4.10.1 Power-On Reset (POR)

During chip power-up the digital core may not work if its supply voltage VDD is below the POR

deassertion level (VPORD). Therefore, signal POR, which forces the other blocks of the device into reset,

is kept high until VDD exceeds VPORD. The MCU will run the start-up sequence after POR deassertion.

The power-on reset is active in all operation modes of VREG_3V3.

23.4.10.2 Low-Voltage Reset (LVR)

For details on low-voltage reset, see Section 23.4.5, âLow-Voltage Reset (LVR)â.

23.4.11 Interrupts

This section describes all interrupts originated by VREG_3V3.

The interrupt vectors requested by VREG_3V3 are listed in Table 23-13. Vector addresses and interrupt

priorities are deï¬ned at MCU level.

MC9S12XE-Family Reference Manual Rev. 1.25

828

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