S912XEG384J3VA Datasheet, PDF (323/1324 Pages) Freescale Semiconductor, Inc – MC9S12XEP100 Reference Manual Covers MC9S12XE Family

Chapter 8 S12X Debug (S12XDBGV3) Module
Table 8-30. DBGXCTL Field Descriptions (continued)
Field
1
SRC
0
COMPE
Description
Determines mapping of comparator to CPU12X or XGATE
0 The comparator is mapped to CPU12X buses
1 The comparator is mapped to XGATE address and data buses
Determines if comparator is enabled
0 The comparator is not enabled
1 The comparator is enabled for state sequence triggers or tag generation
Table 8-31 shows the effect for RWE and RW on the comparison conditions. These bits are not useful for
tagged operations since the trigger occurs based on the tagged opcode reaching the execution stage of the
instruction queue. Thus these bits are ignored if tagged triggering is selected.
Table 8-31. Read or Write Comparison Logic Table
RWE Bit
0
0
1
1
1
1
RW Bit
x
x
0
0
1
1
RW Signal
0
1
0
1
0
1
Comment
RW not used in comparison
RW not used in comparison
Write
No match
No match
Read
8.3.2.8.2 Debug Comparator Address High Register (DBGXAH)
Address: 0x0029
R
W
Reset
7
6
5
4
3
2
1
0
Bit 22
Bit 21
Bit 20
Bit 19
Bit 18
Bit 17
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 8-15. Debug Comparator Address High Register (DBGXAH)
Read: Anytime. See Table 8-29 for visible register encoding.
Write: If DBG not armed. See Table 8-29 for visible register encoding.
0
Bit 16
0
Table 8-32. DBGXAH Field Descriptions
Field
Description
6–0
Bit[22:16]
Comparator Address High Compare Bits — The Comparator address high compare bits control whether the
selected comparator will compare the address bus bits [22:16] to a logic one or logic zero. This register byte is
ignored for XGATE compares.
0 Compare corresponding address bit to a logic zero
1 Compare corresponding address bit to a logic one
MC9S12XE-Family Reference Manual Rev. 1.25
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