S912XEG384J3VA Datasheet, PDF (150/1324 Pages) Freescale Semiconductor, Inc – MC9S12XEP100 Reference Manual Covers MC9S12XE Family

Chapter 2 Port Integration Module (S12XEPIMV1)
Table 2-57. PTJ Register Field Descriptions (continued)
Field
1
PTJ
0
PTJ
Description
Port J general purpose input/output data—Data Register
This pin is associated with the TXD signal of SCI2.
When not used with the alternative function, this pin can be used as general purpose I/O.
If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the
buffered pin input state is read.
Port J general purpose input/output data—Data Register
This pin is associated with the TXD signal of SCI2 and chip select output CS3. The SCI function takes precedence
over the chip select and general purpose I/O function if the SCI2 is enabled. The chip select takes precedence over
the general purpose I/O.
When not used with the alternative function, this pin can be used as general purpose I/O.
If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the
buffered pin input state is read.
2.3.62 Port J Input Register (PTIJ)
Address 0x0269
7
R PTIJ7
6
PTIJ6
5
PTIJ5
4
PTIJ4
3
PTIJ3
2
PTIJ2
W
Reset
u
u
u
u
u
u
= Unimplemented or Reserved
u = Unaffected by reset
Figure 2-60. Port J Input Register (PTIJ)
1. Read: Anytime.
Write:Never, writes to this register have no effect.
Access: User read⁽¹⁾
1
PTIJ1
0
PTIJ0
u
u
Field
7-0
PTIJ
Table 2-58. PTIJ Register Field Descriptions
Description
Port J input data—
This register always reads back the buffered state of the associated pins. This can also be used to detect overload
or short circuit conditions on output pins.
2.3.63 Port J Data Direction Register (DDRJ)
Address 0x026A
R
W
Reset
7
DDRJ7
0
6
DDRJ6
5
DDRJ5
4
DDRJ4
3
DDRJ3
2
DDRJ2
0
0
0
0
0
Figure 2-61. Port J Data Direction Register (DDRJ)
Access: User read/write⁽¹⁾
1
0
DDRJ1
DDRJ0
0
0
MC9S12XE-Family Reference Manual Rev. 1.25
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