S912XEG384J3VA Datasheet, PDF (364/1324 Pages) Freescale Semiconductor, Inc – MC9S12XEP100 Reference Manual Covers MC9S12XE Family

Chapter 10 XGATE (S12XGATEV3)
Table 10-7. XGISP74 Field Descriptions
Field
Description
15–1
Initial Stack Pointer— The XGISP74 register holds the initial value of RISC core register R7, for threads of
XBISP74[15:1] priority 7 to 4.
10.3.1.6 XGATE Initial Stack Pointer for Interrupt Priorities 3 to 1 (XGISP31)
The XGISP31 register is intended to point to the stack region that is used by XGATE channels of priority
3 to 1. Every time a thread of such priority is started, RISC core register R7 will be initialized with the
content of XGISP31.
Module Base +0x0006
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
0
XGISP31[15:1]
W
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 10-8. XGATE Initial Stack Pointer for Interrupt Priorities 3 to 1 (XGISP31)
Read: Anytime
Write: Only if XGATE requests are disabled (XGE = 0) and idle (XGCHID = $00))
Table 10-8. XGISP31 Field Descriptions
Field
Description
15–1
Initial Stack Pointer— The XGISP31 register holds the initial value of RISC core register R7, for threads of
XBISP31[15:1] priority 3 to 1.
10.3.1.7 XGATE Vector Base Address Register (XGVBR)
The Vector Base Address Register (Figure 10-9) determines the location of the XGATE vector block (see
Section Figure 10-23., “XGATE Vector Block).
Module Base +0x0006
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
0
XGVBR[15:1]
W
Reset 1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 10-9. XGATE Vector Base Address Register (XGVBR)
Read: Anytime
Write: Only if XGATE requests are disabled (XGE = 0) and idle (XGCHID = $00))
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