S912XEG384J3VA Datasheet, PDF (683/1324 Pages) Freescale Semiconductor, Inc – MC9S12XEP100 Reference Manual Covers MC9S12XE Family

Chapter 18 Periodic Interrupt Timer (S12PIT24B4CV2)
18.3.0.4 PIT Multiplex Register (PITMUX)
Module Base + 0x0003
7
R
0
W
Reset
0
6
5
4
3
2
0
0
0
PMUX3
PMUX2
0
0
0
0
0
Figure 18-6. PIT Multiplex Register (PITMUX)
Read: Anytime
Write: Anytime
1
PMUX1
0
0
PMUX0
0
Table 18-5. PITMUX Field Descriptions
Field
Description
3:0
PMUX[3:0]
PIT Multiplex Bits for Timer Channel 3:0 — These bits select if the corresponding 16-bit timer is connected to
micro time base 1 or 0. If PMUX is modified, the corresponding 16-bit timer is switched to the other micro time
base immediately.
0 The corresponding 16-bit timer counts with micro time base 0.
1 The corresponding 16-bit timer counts with micro time base 1.
18.3.0.5 PIT Interrupt Enable Register (PITINTE)
Module Base + 0x0004
7
R
0
W
Reset
0
6
5
4
3
2
0
0
0
PINTE3
PINTE2
0
0
0
0
0
Figure 18-7. PIT Interrupt Enable Register (PITINTE)
1
PINTE1
0
0
PINTE0
0
Read: Anytime
Write: Anytime
Table 18-6. PITINTE Field Descriptions
Field
Description
3:0
PINTE[3:0]
PIT Time-out Interrupt Enable Bits for Timer Channel 3:0 — These bits enable an interrupt service request
whenever the time-out flag PTF of the corresponding PIT channel is set. When an interrupt is pending (PTF set)
enabling the interrupt will immediately cause an interrupt. To avoid this, the corresponding PTF flag has to be
cleared first.
0 Interrupt of the corresponding PIT channel is disabled.
1 Interrupt of the corresponding PIT channel is enabled.
MC9S12XE-Family Reference Manual Rev. 1.25
Freescale Semiconductor
683