S912XEG384J3VA Datasheet, PDF (262/1324 Pages) Freescale Semiconductor, Inc – MC9S12XEP100 Reference Manual Covers MC9S12XE Family

Chapter 6 Interrupt (S12XINTV2)
6.1.1 Glossary
The following terms and abbreviations are used in the document.
Table 6-2. Terminology
Term
CCR
DMA
INT
IPL
ISR
MCU
XGATE
IRQ
XIRQ
Meaning
Condition Code Register (in the S12X CPU)
Direct Memory Access
Interrupt
Interrupt Processing Level
Interrupt Service Routine
Micro-Controller Unit
refers to the XGATE co-processor; XGATE is an optional feature
refers to the interrupt request associated with the IRQ pin
refers to the interrupt request associated with the XIRQ pin
6.1.2 Features
• Interrupt vector base register (IVBR)
• One spurious interrupt vector (at address vector base¹ + 0x0010).
• One non-maskable system call interrupt vector request (at address vector base + 0x0012).
• Three non-maskable access violation interrupt vector requests (at address vector base + 0x0014−
0x0018).
• 2–109 I bit maskable interrupt vector requests (at addresses vector base + 0x001A–0x00F2).
• Each I bit maskable interrupt request has a configurable priority level and can be configured to be
handled by either the CPU or the XGATE module².
• I bit maskable interrupts can be nested, depending on their priority levels.
• One X bit maskable interrupt vector request (at address vector base + 0x00F4).
• One non-maskable software interrupt request (SWI) or background debug mode vector request (at
address vector base + 0x00F6).
• One non-maskable unimplemented op-code trap (TRAP) vector (at address vector base + 0x00F8).
• Three system reset vectors (at addresses 0xFFFA–0xFFFE).
• Determines the highest priority XGATE and interrupt vector requests, drives the vector to the
XGATE module or to the bus on CPU request, respectively.
• Wakes up the system from stop or wait mode when an appropriate interrupt request occurs or
whenever XIRQ is asserted, even if X interrupt is masked.
• XGATE can wake up and execute code, even with the CPU remaining in stop or wait mode.
1. The vector base is a 16-bit address which is accumulated from the contents of the interrupt vector base register (IVBR, used
as upper byte) and 0x00 (used as lower byte).
2. The IRQ interrupt can only be handled by the CPU
MC9S12XE-Family Reference Manual Rev. 1.25
262
Freescale Semiconductor