S912XEG384J3VA Datasheet, PDF (458/1324 Pages) Freescale Semiconductor, Inc – MC9S12XEP100 Reference Manual Covers MC9S12XE Family

Chapter 10 XGATE (S12XGATEV3)
XNOR
Logical Exclusive NOR
XNOR
Operation
~(RS1 ^ RS2) ⇒ RD
~(RD ^ IMM16)⇒ RD
(translates to XNOR RD, #IMM16{15:8]; XNOR RD, #IMM16[7:0])
Performs a bit wise logical exclusive NOR between two 16 bit values and stores the result in the destination
register RD.
Remark: Using R0 as a source registers will calculate the one’s complement of the other source register.
Using R0 as both source operands will fill RD with $FFFF.
NOTE
When using immediate addressing mode (XNOR RD, #IMM16), the Z-flag
of the first instruction (XNORL RD, #IMM16[7:0]) is not considered by the
second instruction (XNORH RD, #IMM16[15:8]).
⇒ Don’t rely on the Z-Flag.
CCR Effects
NZVC
∆ ∆ 0—
N: Set if bit 15 of the result is set; cleared otherwise.
Z: Set if the result is $0000; cleared otherwise.
Refer to XNORH instruction for #IMM16 operations.
V: 0; cleared.
C: Not affected.
Code and CPU Cycles
Source Form
XNOR RD, RS1, RS2
XNOR RD, #IMM16
Address
Mode
TRI
IMM8
IMM8
00010
10110
10111
Machine Code
Cycles
RD
RS1
RS2 1 1
P
RD
IMM16[7:0]
P
RD
IMM16[15:8]
P
MC9S12XE-Family Reference Manual Rev. 1.25
458
Freescale Semiconductor