S912XEG384J3VA Datasheet, PDF(84/1324 Page) Freescale Semiconductor, Inc – MC9S12XEP100 Reference Manual Covers MC9S12XE Family

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S912XEG384J3VA Datasheet, PDF (84/1324 Pages) Freescale Semiconductor, Inc – MC9S12XEP100 Reference Manual Covers MC9S12XE Family

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Chapter 1 Device Overview MC9S12XE-Family

Table 1-14. Interrupt Vector Locations (Sheet 4 of 4)

Vector Address(1)

Vector base+ $4E

Vector base + $4C

Vector base+ $4A

Vector base+ $48

Vector base+ $46

Vector base+ $44

Vector base + $42

Vector base+ $40

Vector base + $3E

Vector base + $3C

Vector base+ $18

to

Vector base + $3A

XGATE

Channel

ID(2)

$27

$26

$25

$24

$23

$22

$21

$20

$1F

$1E

Interrupt Source

CCR

Mask

Local Enable

STOP WAIT

Wake up Wake up

TIM timer channel 3

I bit

TIE (C3I)

No

Yes

TIM timer channel 4

I bit

TIE (C4I)

No

Yes

TIM timer channel 5

I bit

TIE (C5I)

No

Yes

TIM timer channel 6

I bit

TIE (C6I)

No

Yes

TIM timer channel 7

I bit

TIE (C7I)

No

Yes

TIM timer overï¬ow

I bit

TSRC2 (TOF)

No

Yes

TIM Pulse accumulator A overï¬ow I bit

PACTL (PAOVI)

No

Yes

TIM Pulse accumulator input edge I bit

PACTL (PAI)

No

Yes

ATD0 Compare Interrupt

I bit ATD0CTL2 (ACMPIE) Yes

Yes

ATD1 Compare Interrupt

I bit ATD1CTL2 (ACMPIE) Yes

Yes

Reserved

Vector base + $16

â

XGATE software error interrupt None

Vector base + $14

â

MPU Access Error

None

Vector base + $12

â

System Call Interrupt (SYS)

â

Vector base + $10

â

Spurious interrupt

â

1. 16 bits vector address based

2. For detailed description of XGATE channel ID refer to XGATE Block Guide

None

None

None

None

No

Yes

No

No

â

â

â

â

1.6.3 Effects of Reset

When a reset occurs, MCU registers and control bits are initialized. Refer to the respective block

descriptions for register reset states.

On each reset, the Flash module executes a reset sequence to load Flash configuration registers and

initialize the buffer RAM EEE partition, if required.

1.6.3.1 Flash Conï¬guration Reset Sequence (Core Hold Phase)

On each reset, the Flash module will hold CPU activity while loading Flash module registers and

conï¬guration from the Flash memory. The duration of this phase is given as tRST in the device electrical

parameter speciï¬cation. If double faults are detected in the reset phase, Flash module protection and

security may be active on leaving reset. This is explained in more detail in the Flash module section.

1.6.3.2 EEE Reset Sequence Phase (Core Active Phase)

During this phase of the reset sequence (following on from the core hold phase) the CPU can execute

instructions while the FTM initialization completes and, if conï¬gured for EEE operation, the EEE RAM

MC9S12XE-Family Reference Manual Rev. 1.25

84

Freescale Semiconductor

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