S912XEG384J3VA Datasheet, PDF (142/1324 Pages) Freescale Semiconductor, Inc – MC9S12XEP100 Reference Manual Covers MC9S12XE Family

Chapter 2 Port Integration Module (S12XEPIMV1)
2.3.52 Port P Interrupt Flag Register (PIFP)
Address 0x025F
R
W
Reset
7
PIFP7
0
1. Read: Anytime.
Write: Anytime.
6
PIFP6
5
PIFP5
4
PIFP4
3
PIFP3
2
PIFP2
0
0
0
0
0
Figure 2-50. Port P Interrupt Flag Register (PIFP)
Access: User read/write⁽¹⁾
1
0
PIFP1
PIFP0
0
0
Field
7-0
PIFP
Table 2-48. PPSP Register Field Descriptions
Description
Port P interrupt flag—
Each flag is set by an active edge on the associated input pin. This could be a rising or a falling edge based on the
state of the PPSP register. To clear this flag, write logic level 1 to the corresponding bit in the PIFP register. Writing
a 0 has no effect.
1 Active edge on the associated bit has occurred (an interrupt will occur if the associated enable bit is set).
0 No active edge pending.
2.3.53 Port H Data Register (PTH)
Address 0x0260
R
W
Altern.
Function
Reset
7
PTH7
SS2
TXD5
0
1. Read: Anytime.
Write: Anytime.
6
PTH6
5
PTH5
4
PTH4
3
PTH3
2
PTH2
SCK2
RXD5
0
MOSI2
MISO2
SS1
SCK1
TXD4
RXD4
TXD7
RXD7
0
0
0
0
Figure 2-51. Port H Data Register (PTH)
Access: User read/write⁽¹⁾
1
0
PTH1
PTH0
MOSI1
TXD6
0
MISO1
RXD6
0
MC9S12XE-Family Reference Manual Rev. 1.25
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