HD6473847RHV Datasheet, PDF (99/546 Pages) Renesas Technology Corp – Renesas 8-Bit Single-Chip Microcomputer H8 Family / H8/300L Super Low Power Series

After executing BSET
Input/output
Pin state
PCR3
PDR3
P37
Input
Low
level
0
0
P36
Input
High
level
0
1
Section 2 CPU
P35
P34
P33
P32
P31
⎯
Output Output Output Output Output ⎯
Low
Low
Low
Low
High ⎯
level level level level level
1
1
1
1
1
1
0
0
0
0
1
1
Description on operation
When the BSET instruction is executed, first the CPU reads port 3.
Since P37 and P36 are input pins, the CPU reads the pin states (low-level and high-level input).
P35 to P31 are output pins, so the CPU reads the value in PDR3. In this example PDR3 has a
value of H'81, but the value read by the CPU is H'41.
Next, the CPU sets bit 1 of the read data to 1, changing the PDR3 data to H'43.
Finally, the CPU writes H'43 to PDR3, completing execution of BSET.
As a result of the BSET instruction, bit 1 in PDR3 becomes 1, and P31 outputs a high-level signal.
However, bits 7 and 6 of PDR3 end up with different values. To prevent this problem, store a copy
of the PDR3 data in a work area in memory. Perform the bit manipulation on the data in the work
area, then write this data to PDR3.
Prior to executing BSET
MOV.B
MOV.B
MOV.B
#81, R0L
R0L, @RAM0
R0L, @PDR3
The PDR3 value (H'81) is written to a work area in
memory (RAM0) as well as to PDR3.
Input/output
Pin state
PCR3
PDR3
RAM0
P37
Input
Low
level
0
1
1
P36
Input
High
level
0
0
0
P35
P34
P33
P32
P31
⎯
Output Output Output Output Output ⎯
Low
Low
Low
Low
Low
⎯
level level level level level
1
1
1
1
1
1
0
0
0
0
0
1
0
0
0
0
0
1
Rev. 7.00 Mar. 08, 2010 Page 67 of 510
REJ09B0024-0700