HD6473847RHV Datasheet, PDF (264/546 Pages) Renesas Technology Corp – Renesas 8-Bit Single-Chip Microcomputer H8 Family / H8/300L Super Low Power Series

Section 9 Timers
9.3.6 Timer F Operating States
The timer F operating states are shown in table 9.4.
Table 9.4 Timer F Operating States
Operating
Mode
Reset
Active Sleep
Watch
Module
Sub-active Sub-sleep Standby Standby
TCF
Reset
Functions^* Functions^* Functions/ Functions/ Functions/ Halted
Halted
Halted^*
Halted^*
Halted^*
OCRF
Reset
Functions Retained Retained Functions
Retained Retained Retained
TCRF
Reset
Functions Retained Retained Functions
Retained Retained Retained
TCSRF
Note: *
Reset
Functions Retained Retained Functions
Retained Retained Retained
When φ_W/4 is selected as the TCF internal clock in active mode or sleep mode, since
the system clock and internal clock are mutually asynchronous, synchronization is
maintained by a synchronization circuit. This results in a maximum count cycle error of
1/φ (s). When the counter is operated in subactive mode, watch mode, or subsleep
mode, φ_W /4 must be selected as the internal clock. The counter will not operate if any
other internal clock is selected.
9.3.7 Usage Notes
The following types of contention and operation can occur when the timer F is used.
16-Bit Timer Mode: In toggle output, TMOFH pin output is toggled when all 16 bits match and a
compare match signal is generated. If a TCRF write by a MOV instruction and generation of the
compare match signal occur simultaneously, TOLH data is output to the TMOFH pin as a result of
the TCRF write. TMOFL pin output is unstable in 16-bit mode, and should not be used; the
TMOFL pin should be used as a port pin.
If an OCRFL write and compare match signal generation occur simultaneously, the compare
match signal is invalid. However, if the written data and the counter value match, a compare
match signal will be generated at that point. As the compare match signal is output in
synchronization with the TCFL clock, a compare match will not result in compare match signal
generation if the clock is stopped.
Compare match flag CMFH is set when all 16 bits match and a compare match signal is generated.
Compare match flag CMFL is set if the setting conditions for the lower 8 bits are satisfied.
Rev. 7.00 Mar. 08, 2010 Page 232 of 510
REJ09B0024-0700