HD6473847RHV Datasheet, PDF (283/546 Pages) Renesas Technology Corp – Renesas 8-Bit Single-Chip Microcomputer H8 Family / H8/300L Super Low Power Series

Section 9 Timers
Mode
Active (high-speed), sleep (high-speed)
Active (medium-speed), sleep (medium-speed)
(φ/16)
(φ/32)
(φ/64)
f_OSC = 1 MHz to 4 MHz
(φ/128)
Watch, subactive, subsleep, standby
(φ_W/2)
φ_W = 32.768 kHz or 38.4 kHz^*2
(φ /4)
W
(φ_W/8)
Notes: 1. Up to 10 MHz in the H8/38004, H8/38002S Group.
2. Does not apply to H8/38104 Group.
Maximum Clock Frequency
Input to AEVH/AEVL Pin
16 MHz^*1
2×f
OSC
f_OSC
1/2 × f_OSC
1/4 × f_OSC
1000 kHz
500 kHz
250 kHz
3. When AEC uses with 16-bit mode, set CUEH in ECCSR to 1 first, set CRCH in ECCSR to 1
second, or set both CUEH and CRCH to 1 at same time before clock input. While AEC is
operating on 16-bit mode, do not change CUEH. Otherwise, ECH will be miscounted up.
4. When ECPWME in AEGSR is 1, the event counter PWM is operating and therefore
ECPWCRH, ECPWCRL, ECPWDRH, and ECPWDRL should not be modified.
When changing the data, the event counter PWM must be halted by clearing ECPWME to 0 in
AEGSR before modifying these registers.
5. The event counter PWM data register and event counter PWM compare register must be set so
that event counter PWM data register < event counter PWM compare register. If the settings
do not satisfy this condition, do not set ECPWME to 1 in AEGSR.
6. As synchronization is established internally when an IRQAEC interrupt is generated, a
maximum error of 1 tcyc will occur between clock halting and interrupt acceptance.
Rev. 7.00 Mar. 08, 2010 Page 251 of 510
REJ09B0024-0700