HD6473847RHV Datasheet, PDF (24/546 Pages) Renesas Technology Corp – Renesas 8-Bit Single-Chip Microcomputer H8 Family / H8/300L Super Low Power Series

Figure 9.3 Write Access to TCF (CPU → TCF) .................................................................. 228
Figure 9.4 Read Access to TCF (TCF → CPU) ................................................................... 229
Figure 9.5 TMOFH/TMOFL Output Timing ....................................................................... 231
Figure 9.6 Clear Interrupt Request Flag when Interrupt Source Generation Signal
Is Valid................................................................................................................ 235
Figure 9.7 Block Diagram of Asynchronous Event Counter................................................ 237
Figure 9.8 Example of Software Processing when Using ECH and ECL
as 16-Bit Event Counter...................................................................................... 246
Figure 9.9 Example of Software Processing when Using ECH and ECL
as 8-Bit Event Counters ...................................................................................... 247
Figure 9.10 Event Counter Operation Waveform .................................................................. 248
Figure 9.11 Example of Clock Control Operation ................................................................. 249
Figure 9.12(1) Block Diagram of Watchdog Timer (H8/38004, H8/38002S Group)................. 252
Figure 9.12(2) Block Diagram of Watchdog Timer (H8/38104 Group) ..................................... 253
Figure 9.13 Example of Watchdog Timer Operation ............................................................. 257
Section 10 Serial Communication Interface 3 (SCI3)
Figure 10.1 Block Diagram of SCI3 ...................................................................................... 260
Figure 10.2 Data Format in Asynchronous Communication.................................................. 277
Figure 10.3 Relationship between Output Clock and Transfer Data Phase
(Asynchronous Mode) (Example with 8-Bit Data, Parity, Two Stop Bits)......... 278
Figure 10.4 Sample SCI3 Initialization Flowchart................................................................. 282
Figure 10.5 Example SCI3 Operation in Transmission in Asynchronous Mode
(8-Bit Data, Parity, One Stop Bit)....................................................................... 283
Figure 10.6 Sample Serial Transmission Flowchart (Asynchronous Mode).......................... 284
Figure 10.7 Example SCI3 Operation in Reception in Asynchronous Mode
(8-Bit Data, Parity, One Stop Bit)....................................................................... 286
Figure 10.8 Sample Serial Data Reception Flowchart (Asynchronous Mode) (1) ................. 287
Figure 10.8 Sample Serial Data Reception Flowchart (Asynchronous Mode) (2) ................. 288
Figure 10.9 Data Format in Clocked Synchronous Communication...................................... 289
Figure 10.10 Example of SCI3 Operation in Transmission in Clocked Synchronous Mode ... 291
Figure 10.11 Sample Serial Transmission Flowchart (Clocked Synchronous Mode).............. 292
Figure 10.12 Example of SCI3 Reception Operation in Clocked Synchronous Mode............. 293
Figure 10.13 Sample Serial Reception Flowchart (Clocked Synchronous Mode) ................... 294
Figure 10.14 Sample Flowchart of Simultaneous Serial Transmit and Receive Operations
(Clocked Synchronous Mode) ............................................................................ 296
Figure 10.15(a) RDRF Setting and RXI Interrupt ........................................................................ 298
Figure 10.15(b) TDRE Setting and TXI Interrupt ........................................................................ 299
Figure 10.15(c) TEND Setting and TEI Interrupt......................................................................... 299
Figure 10.16 Receive Data Sampling Timing in Asynchronous Mode.................................... 301
Figure 10.17 Relation between RDR Read Timing and Data .................................................. 302
Rev. 7.00 Mar. 08, 2010 Page xxii of xxx
REJ09B0024-0700