HD6473847RHV Datasheet, PDF (149/546 Pages) Renesas Technology Corp – Renesas 8-Bit Single-Chip Microcomputer H8 Family / H8/300L Super Low Power Series

Section 5 Power-Down Modes
• CKSTPR2
Initial
Bit
Bit Name Value R/W Description
7
LVDCKSTP 1
R/W LVD module standby
The LVD module enters standby status when this bit is
cleared to 0.
Note: On products other than the H8/38104 Group,
this bit is reserved like bits 6 and 5.
6, 5 ⎯
All 1
4
PW2CKSTP 1
⎯
Reserved
R/W^*3 PWM2 Module Standby
PWM2 enters standby mode when this bit is cleared to
0.
3
AECKSTP 1
R/W Asynchronous Event Counter Module Standby
2
WDCKSTP 1
R/W^*4
Asynchronous event counter enters standby mode
when this bit is cleared to 0
Watchdog Timer Module Standby
Watchdog timer enters standby mode when this bit is
cleared to 0
1
PW1CKSTP 1
R/W PWM1 Module Standby
PWM1 enters standby mode when this bit is cleared to
0
0
LDCKSTP 1
R/W LCD Module Standby
LCD controller/driver enters standby mode when this bit
is cleared to 0
Notes: 1. When the SCI module standby is set, all registers in the SCI3 enter the reset state.
2. When the timer A module standby is set, the TMA3 bit in TMA cannot be rewritten.
When the TMA3 bit is rewritten, the TACKSTP bit in CKSTPR1 should be set to 1 in
advance.
3. This bit cannot be read or written in the H8/3802 Group.
4. This bit cannot be read or written in the H8/3802 Group. This bit is valid when the
WDON bit in TCSRW is 0. If this bit is cleared to 0 while the WDON bit is set to 1 (while
the watchdog timer is operating), this bit is cleared to 0. However, the watchdog timer
does not enter module standby mode and continues operating. When the watchdog
timer stops operating and the WDON bit is cleared to 0 by software, this bit is valid and
the watchdog timer enters module standby mode.
Rev. 7.00 Mar. 08, 2010 Page 117 of 510
REJ09B0024-0700