HD6473847RHV Datasheet, PDF (87/546 Pages) Renesas Technology Corp – Renesas 8-Bit Single-Chip Microcomputer H8 Family / H8/300L Super Low Power Series

Section 2 CPU
Immediate—#xx:8/#xx:16
The instruction contains an 8-bit operand (#xx:8) in its second byte, or a 16-bit operand (#xx:16)
in its third and fourth bytes. Only MOV.W instructions can contain 16-bit immediate values.
The ADDS and SUBS instructions implicitly contain the value 1 or 2 as immediate data. Some bit
manipulation instructions contain 3-bit immediate data in the second or fourth byte of the
instruction, specifying a bit number.
Program-Counter Relative—@(d:8, PC)
This mode is used in the Bcc and BSR instructions. An 8-bit displacement in byte 2 of the
instruction code is sign-extended to 16 bits and added to the program counter contents to generate
a branch destination address. The possible branching range is –126 to +128 bytes (–63 to +64
words) from the current address. The displacement should be an even number.
Memory Indirect—@@aa:8
This mode can be used by the JMP and JSR instructions. The second byte of the instruction code
specifies an 8-bit absolute address. The word located at this address contains the branch
destination address. The upper 8 bits of the absolute address are assumed to be 0 (H'00), so the
address range is from H'0000 to H'00FF (0 to 255). Note that with the H8/300L Series, the lower
end of the address area is also used as a vector area. See section 3.1, Exception Sources and
Vector Address, for details on the vector area.
If an odd address is specified as a branch destination or as the operand address of a MOV.W
instruction, the least significant bit is regarded as 0, causing word access to be performed at the
address preceding the specified address. See section 2.4.2, Memory Data Formats, for further
information.
Rev. 7.00 Mar. 08, 2010 Page 55 of 510
REJ09B0024-0700