HD6473847RHV Datasheet, PDF (180/546 Pages) Renesas Technology Corp – Renesas 8-Bit Single-Chip Microcomputer H8 Family / H8/300L Super Low Power Series

Section 6 ROM
6.6.2 Flash Memory Control Register 2 (FLMCR2)
FLMCR2 is a register that displays the state of flash memory programming/erasing. FLMCR2 is a
read-only register, and should not be written to.
Initial
Bit
Bit Name Value R/W Description
7
FLER
0
R
Flash Memory Error
Indicates that an error has occurred during an operation
on flash memory (programming or erasing). When flash
memory goes to the error-protection state, this bit is set to
1.
See section 6.9.3, Error Protection, for details.
6 to 0 —
All 0
—
Reserved
These bits are always read as 0.
6.6.3 Erase Block Register (EBR)
EBR specifies the flash memory erase area block. EBR is initialized to H'00 when the SWE bit in
FLMCR1 is 0. Do not set more than one bit at a time, as this will cause all the bits in EBR to be
automatically cleared to 0.
Initial
Bit
Bit Name Value R/W Description
7 to 5 —
All 0
—
Reserved
These bits are always read as 0.
4
EB4
0
R/W When this bit is set to 1, 28 kbytes of H'1000 to H'7FFF
will be erased in the HD64F38004 and HD64F38104.
When this bit is set to 1, 12 kbytes of H'1000 to H'3FFF
will be erased in the HD64F38002 and HD64F38102.
3
EB3
0
R/W When this bit is set to 1, 1 kbyte of H'0C00 to H'0FFF will
be erased.
2
EB2
0
R/W When this bit is set to 1, 1 kbyte of H'0800 to H'0BFF will
be erased.
1
EB1
0
R/W When this bit is set to 1, 1 kbyte of H'0400 to H'07FF will
be erased.
0
EB0
0
R/W When this bit is set to 1, 1 kbyte of H'0000 to H'03FF will
be erased.
Rev. 7.00 Mar. 08, 2010 Page 148 of 510
REJ09B0024-0700