HD6473847RHV Datasheet, PDF (288/546 Pages) Renesas Technology Corp – Renesas 8-Bit Single-Chip Microcomputer H8 Family / H8/300L Super Low Power Series

Section 9 Timers
Initial
Bit
Bit Name Value R/W Description
7 to 4 —
All 1
—
This bit is reserved. It is always read as 1.
3
CKS3
1
R/W Clock Select 3 to 0
2
CKS2
1
R/W Selects the clock input to TCWD.
1
CKS1
1
0
CKS0
1
R/W 1000: Internal clock: counting on φ/64
R/W ^{1001: Internal clock: counting on φ/128}
1010: Internal clock: counting on φ/256
1011: Internal clock: counting on φ/512
1100: Internal clock: counting on φ/1,024
1101: Internal clock: counting on φ/2,048
1110: Internal clock: counting on φ/4,096
1111: Internal clock: counting on φ/8,192
0XXX: On-chip oscillator
See section 17, Electrical Characteristics, for information
on the overflow period of the on-chip oscillator.
Legend: X: Don't care
9.5.3 Operation
The watchdog timer is provided with an 8-bit counter. The input clock is selected by the WDCKS
bit in the port mode register 2 (PMR2)*: On the H8/38004, H8/38002S Group, φ/8192 is selected
when the WDCKS bit is cleared to 0, and φw/32 when set to 1. On the H8/38104 Group, the clock
specified by timer mode register W (TMW) is selected when WDCKS is cleared to 0, and φw/32
is selected when WDCKS is set to 1. If 1 is written to WDON while writing 0 to B2WI when the
TCSRWE bit in TCSRW is set to 1, TCW begins counting up. (To operate the watchdog timer,
two write accesses to TCSRW are required. However, on the H8/38104 Group, TCW begins
counting up even if no write access occurs, because WDON is set to 1 when the reset is cleared.)
When a clock pulse is input after the TCW count value has reached H'FF, the watchdog timer
overflows and an internal reset signal is generated. The internal reset signal is output for a period
of
512
φ
osc
clock
cycles.
TCW
is
a
writable
counter,
and
when
a
value
is
set
in
TCW,
the
count-up
starts from that value. An overflow period in the range of 1 to 256 input clock cycles can therefore
be set, according to the TCW set value.
Note: * For details, refer to section 8.1.5, Port Mode Register 2 (PMR2).
Rev. 7.00 Mar. 08, 2010 Page 256 of 510
REJ09B0024-0700