HD6473847RHV Datasheet, PDF (488/546 Pages) Renesas Technology Corp – Renesas 8-Bit Single-Chip Microcomputer H8 Family / H8/300L Super Low Power Series

Appendix A Instruction Set
A.3 Number of Execution States
The status of execution for each instruction of the H8/300L CPU and the method of calculating the
number of states required for instruction execution are shown below. Table A.4 shows the number
of cycles of each type occurring in each instruction, such as instruction fetch and data read/write.
Table A.3 shows the number of states required for each cycle. The total number of states required
for execution of an instruction can be calculated by the following expression:
Execution states = I × S_I + J × S_J + K × S_K + L × S_L + M × S_M + N × S_N
Examples: When an instruction is fetched from the on-chip ROM, and the on-chip RAM is
accessed.
BSET #0, @FF00
From table A.4:
I = L = 2, J = K = M = N= 0
From table A.3:
S_I = 2, S_L = 2
Number of states required for execution = 2 × 2 + 2 × 2 = 8
When an instruction is fetched from the on-chip ROM, a branch address is read from the on-chip
ROM, and the on-chip RAM is used for stack area.
JSR @@ 30
From table A.4:
I = 2, J = K = 1, L = M = N = 0
From table A.3:
S_I = S_J = S_K = 2
Number of states required for execution = 2 × 2 + 1 × 2+ 1 × 2 = 8
Rev. 7.00 Mar. 08, 2010 Page 456 of 510
REJ09B0024-0700