HD6473847RHV Datasheet, PDF (94/546 Pages) Renesas Technology Corp – Renesas 8-Bit Single-Chip Microcomputer H8 Family / H8/300L Super Low Power Series

Section 2 CPU
Three-State Access to On-Chip Peripheral Modules:
Figure 2.14 shows the operation timing in the case of three-state access to an on-chip peripheral
module.
φ or φ _SUB
T₁ state
Bus cycle
T₂ state
T₃ state
Internal
address bus
Internal
read signal
Internal
data bus
(read access)
Internal
write signal
Internal
data bus
(write access)
Address
Read data
Write data
Figure 2.14 On-Chip Peripheral Module Access Cycle (3-State Access)
Rev. 7.00 Mar. 08, 2010 Page 62 of 510
REJ09B0024-0700