HD6473847RHV Datasheet, PDF (76/546 Pages) Renesas Technology Corp – Renesas 8-Bit Single-Chip Microcomputer H8 Family / H8/300L Super Low Power Series

Section 2 CPU
2.5.3 Logic Operations Instructions
Table 2.5 describes the logic operations instructions.
Table 2.5 Logic Operations Instructions
Instruction Size^* Function
AND
B
Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd
Performs a logical AND operation on a general register and another
general register or immediate data.
OR
B
Rd ∨ Rs → Rd, Rd ∨ #IMM → Rd
Performs a logical OR operation on a general register and another
general register or immediate data.
XOR
B
Rd ⊕ Rs → Rd, Rd ⊕ #IMM → Rd
Performs a logical exclusive OR operation on a general register and
another general register or immediate data.
NOT
B
¬ (Rd) → (Rd)
Obtains the one's complement (logical complement) of general register
contents.
Note: * Refers to the operand size.
B: Byte
2.5.4 Shift Instructions
Table 2.6 describes the shift instructions.
Table 2.6 Shift Instructions
Instruction Size^* Function
SHAL
SHAR
B
Rd (shift) → Rd
Performs an arithmetic shift on general register contents.
SHLL
SHLR
B
Rd (shift) → Rd
Performs a logical shift on general register contents.
ROTL
ROTR
B
Rd (rotate) → Rd
Rotates general register contents.
ROTXL
B
ROTXR
Rd (rotate) → Rd
Rotates general register contents through the carry flag.
Note: * Refers to the operand size.
B: Byte
Rev. 7.00 Mar. 08, 2010 Page 44 of 510
REJ09B0024-0700