HD6473847RHV Datasheet, PDF (263/546 Pages) Renesas Technology Corp – Renesas 8-Bit Single-Chip Microcomputer H8 Family / H8/300L Super Low Power Series

φ
Count input clock
Section 9 Timers
TCF
N
OCRF
Compare match signal
N+1
N
N
N+1
N
TMOFH, TMOFL
Figure 9.5 TMOFH/TMOFL Output Timing
TCF Clear Timing: TCF can be cleared by a compare match with OCRF.
Timer Overflow Flag (OVF) Set Timing: OVF is set to 1 when TCF overflows from H'FFFF to
H'0000.
Compare Match Flag Set Timing: The compare match flag (CMFH or CMFL) is set to 1 when
the TCF and OCRF values match. The compare match signal is generated in the last state during
which the values match (when TCF is updated from the matching value to a new value). When
TCF matches OCRF, the compare match signal is not generated until the next counter clock.
Rev. 7.00 Mar. 08, 2010 Page 231 of 510
REJ09B0024-0700