HD6473847RHV Datasheet, PDF (109/546 Pages) Renesas Technology Corp – Renesas 8-Bit Single-Chip Microcomputer H8 Family / H8/300L Super Low Power Series

Section 3 Exception Handling
3.2 Register Descriptions
Interrupts are controlled by the following registers.
• Interrupt edge select register (IEGR)
• Interrupt enable register 1 (IENR1)
• Interrupt enable register 2 (IENR2)
• Interrupt request register 1 (IRR1)
• Interrupt request register 2 (IRR2)
• Wakeup interrupt request register (IWPR)
• Wakeup edge select register (WEGR)
3.2.1 Interrupt Edge Select Register (IEGR)
IEGR selects the direction of an edge that generates interrupt requests of pins and IRQ1 and IRQ0.
Initial
Bit
Bit Name Value R/W Description
7 to 5 ⎯
All 1
⎯
Reserved
These bits are always read as 1.
4 to 2 ⎯
⎯
W
Reserved
The write value should always be 0.
1
IEG1
0
R/W IRQ1 and IRQ0 Edge Select
0
IEG0
0
R/W 0: Falling edge of IRQn pin input is detected
1: Rising edge of IRQn pin input is detected
(n = 1 or 0)
Rev. 7.00 Mar. 08, 2010 Page 77 of 510
REJ09B0024-0700