HD6473847RHV Datasheet, PDF (302/546 Pages) Renesas Technology Corp – Renesas 8-Bit Single-Chip Microcomputer H8 Family / H8/300L Super Low Power Series

Section 10 Serial Communication Interface 3 (SCI3)
Bit
3
2
1
0
Note:
Initial
Bit Name Value R/W Description
PER
0
R/(W)^* Parity Error
[Setting condition]
• When a parity error is generated during reception
[Clearing condition]
• When 0 is written to PER after reading PER = 1
When bit RE in SCR3 is cleared to 0, bit PER is not
affected and retains its previous state.
Receive data in which a parity error has occurred is still
transferred to RDR, but bit RDRF is not set. Reception
cannot be continued with bit PER set to 1. In clocked
synchronous mode, neither transmission nor reception is
possible when bit PER is set to 1.
TEND
1
R
Transmit End
[Setting conditions]
• When the TE bit in SCR3 is 0
• When TDRE = 1 at transmission of the last bit of a 1-
byte serial transmit character
[Clearing conditions]
• When 0 is written to TDRE after reading TDRE = 1
• When the transmit data is written to TDR
MPBR
0
R
Reserved
It's a reserved read-only bit.
MPBT
0
R/W Reserved
The write value should always be 0.
* Only 0 can be written for clearing a flag.
Rev. 7.00 Mar. 08, 2010 Page 270 of 510
REJ09B0024-0700