HD6473847RHV Datasheet, PDF (100/546 Pages) Renesas Technology Corp – Renesas 8-Bit Single-Chip Microcomputer H8 Family / H8/300L Super Low Power Series

Section 2 CPU
BSET instruction executed
BSET #1, @RAM0
The BSET instruction is executed designating the PDR3
work area (RAM0).
After executing BSET
MOV.B @RAM0, R0L
MOV.B R0L, @PDR3
The work area (RAM0) value is written to PDR3.
Input/output
Pin state
PCR3
PDR3
RAM0
P37
Input
Low
level
0
1
1
P36
Input
High
level
0
0
0
P35
P34
P33
P32
P31
⎯
Output Output Output Output Output ⎯
Low
Low
Low
Low
High ⎯
level level level level level
1
1
1
1
1
1
0
0
0
0
1
1
0
0
0
0
1
1
Bit Manipulation in Register Containing Write-Only Bit
Example 3: BCLR instruction executed designating PCR3
P37 and P36 are input pins, with a low-level signal input at P37 and a high-level signal input at
P36. P35 to P31 are output pins that output low-level signals.
An example of setting the P31 pin as an input pin by the BCLR instruction is shown below. It is
assumed that a high-level signal will be input to this input pin.
Prior to executing BCLR
Input/output
Pin state
PCR3
PDR3
P37
Input
Low
level
0
1
P36
Input
High
level
0
0
P35
P34
P33
P32
P31
⎯
Output Output Output Output Output ⎯
Low
Low
Low
Low
Low
⎯
level level level level level
1
1
1
1
1
1
0
0
0
0
0
1
Rev. 7.00 Mar. 08, 2010 Page 68 of 510
REJ09B0024-0700