HD6473847RHV Datasheet, PDF (252/546 Pages) Renesas Technology Corp – Renesas 8-Bit Single-Chip Microcomputer H8 Family / H8/300L Super Low Power Series

Section 9 Timers
9.2.3 Operation
Interval Timer Operation: When bit TMA3 in TMA is cleared to 0, the timer A functions as an
8-bit interval timer.
Upon reset, TCA is cleared to H'00 and bit TMA3 is cleared to 0, so up-counting of the timer A
resume immediately as an interval timer. The clock input to timer A is selected by bits TMA2 to
TMA0 in TMA; any of eight internal clock signals output by prescaler S can be selected.
After the count value in TCA reaches H'FF, the next clock signal input causes timer A to
overflow, setting bit IRRTA to 1 in interrupt Flag Register 1 (IRR1). If IENTA = 1 in the interrupt
enable register 1 (IENR1), a CPU interrupt is requested. At overflow, TCA returns to H'00 and
starts counting up again. In this mode the timer A functions as an interval timer that generates an
overflow output at intervals of 256 input clock pulses.
Clock Time Base Operation: When bit TMA3 in TMA is set to 1, the timer A functions as a
clock-timer base by counting clock signals output by prescaler W. The overflow period of timer A
is set by bits TMA1 and TMA0 in TMA. A choice of four periods is available. In clock time base
operation (TMA3 = 1), setting bit TMA2 to 1 clears both TCA and prescaler W to H'00.
9.2.4 Timer A Operating States
Table 9.2 summarizes the timer A operating states.
Table 9.2 Timer A Operating States
Operating Mode Reset
Active
Sleep
Watch
Sub-active Sub-sleep Standby
Module
Standby
TCA Interval Reset
Functions Functions Halted
Halted
Halted
Halted
Halted
Clock
Reset
time base
Functions^* Functions^* Functions Functions Functions Halted
Halted
TMA
Reset
Functions Retained Retained Functions Retained Retained Retained
Note: * When the clock time base function is selected as the internal clock of TCA in active
mode or sleep mode, the internal clock is not synchronous with the system clock, so it
is synchronized by a synchronizing circuit. This may result in a maximum error of 1/φ (s)
in the count cycle.
Rev. 7.00 Mar. 08, 2010 Page 220 of 510
REJ09B0024-0700