HD6473847RHV Datasheet, PDF (349/546 Pages) Renesas Technology Corp – Renesas 8-Bit Single-Chip Microcomputer H8 Family / H8/300L Super Low Power Series

Section 12 A/D Converter
12.3.3 A/D Start Register (ADSR)
ADSR starts and stops the A/D conversion.
Initial
Bit
Bit Name Value R/W Description
7
ADSF
6 to 0 ⎯
0
R/W When this bit is set to 1, A/D conversion is started. When
conversion is completed, the converted data is set in
ADRRH and ADRRL and at the same time this bit is
cleared to 0. If this bit is written to 0, A/D conversion can
be forcibly terminated.
All 1 ⎯
Reserved
These bits are always read as 1 and cannot be modified.
12.4 Operation
The A/D converter operates by successive approximation with 10-bit resolution. When changing
the conversion time or analog input channel, in order to prevent incorrect operation, first clear the
bit ADSF to 0 in ADSR.
12.4.1 A/D Conversion
1. A/D conversion is started from the selected channel when the ADSF bit in ADSR is set to 1,
according to software.
2. When A/D conversion is completed, the result is transferred to the A/D result register.
3. On completion of conversion, the IRRAD flag in IRR2 is set to 1. If the IENAD bit in IENR2
is set to 1 at this time, an A/D conversion end interrupt request is generated.
4. The ADSF bit remains set to 1 during A/D conversion. When A/D conversion ends, the ADSF
bit is automatically cleared to 0 and the A/D converter enters the wait state.
Rev. 7.00 Mar. 08, 2010 Page 317 of 510
REJ09B0024-0700