HD6473847RHV Datasheet, PDF (155/546 Pages) Renesas Technology Corp – Renesas 8-Bit Single-Chip Microcomputer H8 Family / H8/300L Super Low Power Series

Section 5 Power-Down Modes
When the RES pin goes low, the CPU goes into the reset state and sleep mode is cleared. Since an
interrupt request signal is synchronous with the system clock, the maximum time of 2/φ (s) may be
delayed from the point at which an interrupt request signal occurs until the interrupt exception
handling is started.
Furthermore, it sometimes operates with half state early timing at the time of transition to sleep
(medium-speed) mode.
5.2.2 Standby Mode
In standby mode, the clock pulse generator stops, so the CPU and on-chip peripheral modules stop
functioning. However, as long as the rated voltage is supplied, the contents of CPU registers, on-
chip RAM, and some on-chip peripheral module registers are retained. On-chip RAM contents
will be retained as long as the voltage set by the RAM data retention voltage is provided. The I/O
ports go to the high-impedance state.
Standby mode is cleared by an interrupt. When an interrupt is requested, the system clock pulse
generator starts. After the time set in bits STS2 to STS0 in SYSCR1 has elapsed, standby mode is
cleared and interrupt exception handling starts. After standby mode is cleared, a transition is made
to active (high-speed) or active (medium-speed) mode according to the MSON bit in SYSCR2.
Standby mode is not cleared if the I bit in CCR is set to 1 or the requested interrupt is disabled by
the interrupt enable bit.
When the RES pin goes low, the system clock pulse generator starts. Since system clock signals
are supplied to the entire chip as soon as the system clock pulse generator starts functioning, the
RES pin must be kept low until the pulse generator output stabilizes. After the pulse generator
output has stabilized, the CPU starts reset exception handling if the RES pin is driven high.
5.2.3 Watch Mode
In watch mode, the system clock oscillator and CPU operation stop and on-chip peripheral mod-
ules stop functioning except for the timer A, timer F, asynchronous event counter, and LCD con-
troller/driver. However, as long as the rated voltage is supplied, the contents of CPU registers,
some on-chip peripheral module registers, and on-chip RAM are retained. The I/O ports retain
their state before the transition.
Watch mode is cleared by an interrupt. When an interrupt is requested, watch mode is cleared and
interrupt exception handling starts. When watch mode is cleared by an interrupt, a transition is
made to active (high-speed) mode, active (medium-speed) mode, or subactive mode depending on
the settings of the LSON bit in SYSCR1 and the MSON bit in SYSCR2. When the transition is
made to active mode, after the time set in bits STS2 to STS0 in SYSCR1 has elapsed, interrupt
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