HD6473847RHV Datasheet, PDF (277/546 Pages) Renesas Technology Corp – Renesas 8-Bit Single-Chip Microcomputer H8 Family / H8/300L Super Low Power Series

Section 9 Timers
Event Counter L (ECL): ECL is an 8-bit read-only up-counter that operates as an independent 8-
bit event counter. ECL also operates as the lower 8-bit up-counter of a 16-bit event counter
configured in combination with ECH.
Initial
Bit
Bit Name Value R/W Description
7
ECL7
0
6
ECL6
0
5
ECL5
0
R
Either the external asynchronous event AEVL pin, φ/2,
R
φ/4, or φ/8 can be selected as the input clock source. ECL
can be cleared to H'00 by software.
R
4
ECL4
0
R
3
ECL3
0
R
2
ECL2
0
R
1
ECL1
0
R
0
ECL0
0
R
9.4.4 Operation
16-Bit Counter Operation: When bit CH2 is cleared to 0 in ECCSR, ECH and ECL operate as a
16-bit event counter.
Any of four input clock sources—φ/2, φ/4, φ/8, or AEVL pin input—can be selected by means of
bits ACKL1 and ACKL0 in ECCR.
When AEVL pin input is selected, input sensing is selected with bits ALEGS1 and ALEGS0.
The input clock is enabled only when IRQAEC is high or IECPWM is high. When IRQAEC is
low or IECPWM is low, the input clock is not input to the counter, which therefore does not
operate. Figure 9.8 shows an example of the software processing when ECH and ECL are used as
a 16-bit event counter.
Rev. 7.00 Mar. 08, 2010 Page 245 of 510
REJ09B0024-0700