HD6473847RHV Datasheet, PDF (350/546 Pages) Renesas Technology Corp – Renesas 8-Bit Single-Chip Microcomputer H8 Family / H8/300L Super Low Power Series

Section 12 A/D Converter
12.4.2 Operating States of A/D Converter
Table 12.2 shows the operating states of the A/D converter.
Table 12.2 Operating States of A/D Converter
Operating
Mode
Reset
Active Sleep
AMR
Reset
Functions Functions
ADSR
Reset
Functions Functions
ADRRH
Retained^* Functions Functions
ADRRL
Retained^* Functions Functions
Note: * Undefined in a power-on reset.
Watch
Retained
Reset
Retained
Retained
Sub-active Sub-sleep Standby
Retained Retained Retained
Reset
Reset
Reset
Retained Retained Retained
Retained Retained Retained
Module
Standby
Retained
Reset
Retained
Retained
12.5 Example of Use
An example of how the A/D converter can be used is given below, using channel 1 (pin AN1) as
the analog input channel. Figure 12.2 shows the operation timing.
1. Bits CH3 to CH0 in the A/D mode register (AMR) are set to 0101, making pin AN1 the
analog input channel. A/D interrupts are enabled by setting bit IENAD to 1, and A/D
conversion is started by setting bit ADSF to 1.
2. When A/D conversion is completed, bit IRRAD is set to 1, and the A/D conversion result is
stored in ADRRH and ADRRL. At the same time bit ADSF is cleared to 0, and the A/D
converter goes to the idle state.
3. Bit IENAD = 1, so an A/D conversion end interrupt is requested.
4. The A/D interrupt handling routine starts.
5. The A/D conversion result is read and processed.
6. The A/D interrupt handling routine ends.
If bit ADSF is set to 1 again afterward, A/D conversion starts and steps 2 through 6 take place.
Figures 12.3 and 12.4 show flowcharts of procedures for using the A/D converter.
Rev. 7.00 Mar. 08, 2010 Page 318 of 510
REJ09B0024-0700