HD6473847RHV Datasheet, PDF (318/546 Pages) Renesas Technology Corp – Renesas 8-Bit Single-Chip Microcomputer H8 Family / H8/300L Super Low Power Series

Section 10 Serial Communication Interface 3 (SCI3)
Serial
data
Start
bit
Receive
data
Parity Stop Start
bit bit bit
Receive
data
Parity Stop Mark state
bit bit (idle state)
1 0 D0 D1
D7 0/1 1 0 D0 D1
D7 0/1 0
1
1 frame
1 frame
RDRF
FER
LSI
operation
User
processing
RXI request RDRF
cleared to 0
RDR data read
0 stop bit
detected
ERI request in
response to
framing error
Framing error
processing
Figure 10.7 Example SCI3 Operation in Reception in Asynchronous Mode
(8-Bit Data, Parity, One Stop Bit)
Table 10.10 shows the states of the SSR status flags and receive data handling when a receive
error is detected. If a receive error is detected, the RDRF flag retains its state before receiving
data. Reception cannot be resumed while a receive error flag is set to 1. Accordingly, clear the
OER, FER, PER, and RDRF bits to 0 before resuming reception. Figure 10.8 shows a sample
flowchart for serial data reception.
Table 10.10 SSR Status Flags and Receive Data Handling
SSR Status Flag
RDRF^* OER
FER
PER
Receive Data
Receive Error Type
1
1
0
0
Lost
Overrun error
0
0
1
0
Transferred to RDR Framing error
0
0
0
1
Transferred to RDR Parity error
1
1
1
0
Lost
Overrun error + framing error
1
1
0
1
Lost
Overrun error + parity error
0
0
1
1
Transferred to RDR Framing error + parity error
1
1
1
1
Lost
Overrun error + framing error +
parity error
Note: * The RDRF flag retains the state it had before data reception. However, note that if RDR
is read after an overrun error has occurred in a frame because reading of the receive
data in the previous frame was delayed, the RDRF flag will be cleared to 0.
Rev. 7.00 Mar. 08, 2010 Page 286 of 510
REJ09B0024-0700