HD6473847RHV Datasheet, PDF (328/546 Pages) Renesas Technology Corp – Renesas 8-Bit Single-Chip Microcomputer H8 Family / H8/300L Super Low Power Series

Section 10 Serial Communication Interface 3 (SCI3)
Start transmission/reception
Set SPC32 bit in SPCR to 1
[1] Read SSR and check that the TDRE
flag is set to 1, then write transmit
data to TDR.
Read TDRE flag in SSR
[1]
When data is written to TDR, the
TDRE flag is automatically cleared to
No
TDRE = 1
0.
[2] Read SSR and check that the RDRF
flag is set to 1, then read the receive
Yes
data in RDR.
When data is read from RDR, the
RDRF flag is automatically cleared to
Write transmit data to TDR
0.
[3] To continue serial transmission/
reception, before the MSB (bit 7) of
the current frame is received, finish
Read OER flag in SSR
reading the RDRF flag, reading RDR.
Also, before the MSB (bit 7) of the
OER = 1
Yes
[4]
current frame is transmitted, read 1
from the TDRE flag to confirm that
writing is possible. Then write data to
TDR.
No
Error processing
When data is written to TDR, the
TDRE flag is automatically cleared to
Read RDRF flag in SSR
[2]
0. When data is read from RDR, the
RDRF flag is automatically cleared to
0.
No
RDRF = 1
[4] If an overrun error occurs, read the
OER flag in SSR, and after
performing the appropriate error
Yes
processing, clear the OER flag to 0.
Transmission/reception cannot be
Read receive data in RDR
resumed if the OER flag is set to 1.
For overrun error processing, see
figure 10.13.
Yes
All data received?
[3]
No
Clear TE and RE bits in SCR to 0
<End>
Figure 10.14 Sample Flowchart of Simultaneous Serial Transmit and Receive Operations
(Clocked Synchronous Mode)
Rev. 7.00 Mar. 08, 2010 Page 296 of 510
REJ09B0024-0700