HD6473847RHV Datasheet, PDF (258/546 Pages) Renesas Technology Corp – Renesas 8-Bit Single-Chip Microcomputer H8 Family / H8/300L Super Low Power Series

Section 9 Timers
Timer Control Status Register F (TCSRF): TCSRF performs counter clear selection, overflow
flag setting, and compare match flag setting, and controls enabling of overflow interrupt requests.
Initial
Bit
Bit Name Value R/W Description
7
OVFH
0
R/W^* Timer Overflow Flag H
[Setting condition]
When TCFH overflows from H’FF to H’00
[Clearing condition]
6
CMFH
0
When this bit is written to 0 after reading OVFH = 1
R/W^* Compare Match Flag H
This is a status flag indicating that TCFH has matched
OCRFH.
[Setting condition]
When the TCFH value matches the OCRFH value
[Clearing condition]
When this bit is written to 0 after reading CMFH = 1
5
OVIEH 0
R/W Timer Overflow Interrupt Enable H
Selects enabling or disabling of interrupt generation when
TCFH overflows.
0: TCFH overflow interrupt request is disabled
1: TCFH overflow interrupt request is enabled
4
CCLRH 0
R/W Counter Clear H
In 16-bit mode, this bit selects whether TCF is cleared
when TCF and OCRF match. In 8-bit mode, this bit
selects whether TCFH is cleared when TCFH and
OCRFH match.
In 16-bit mode:
0: TCF clearing by compare match is disabled
1: TCF clearing by compare match is enabled
In 8-bit mode:
0: TCFH clearing by compare match is disabled
1: TCFH clearing by compare match is enabled
Rev. 7.00 Mar. 08, 2010 Page 226 of 510
REJ09B0024-0700