HD6473847RHV Datasheet, PDF (112/546 Pages) Renesas Technology Corp – Renesas 8-Bit Single-Chip Microcomputer H8 Family / H8/300L Super Low Power Series

Section 3 Exception Handling
3.2.4 Interrupt Request Register 1 (IRR1)
IRR1 is a status flag register for timer A, IRQAEC, IRQ1, and IRQ0 interrupt requests. The
corresponding flag is set to 1 when an interrupt request occurs. The flags are not cleared
automatically when an interrupt is accepted. It is necessary to write 0 to clear each flag.
Bit
7
6
5
4, 3
2
1
0
Note:
Initial
Bit Name Value
IRRTA 0
R/W Description
R/W^* _{Timer A Interrupt Request Flag}
[Setting condition]
When the timer A counter value overflows
[Clearing condition]
When IRRTA = 1, it is cleared by writing 0
⎯
⎯
W
Reserved
The write value should always be 0.
⎯
1
⎯
Reserved
This bit is always read as 1 and cannot be modified.
⎯
⎯
W
Reserved
IRREC2 0
The write value should always be 0.
R/W^* _{IRQAEC Interrupt Request Flag}
[Setting condition]
When pin IRQAEC is designated for interrupt input and
the designated signal edge is detected
[Clearing condition]
IRRl1
0
IRRl0
0
R/W^*
R/W^*
When IRREC2 = 1, it is cleared by writing 0
IRQ1 and IRQ0 Interrupt Request Flag
[Setting condition]
When pin IRQn is designated for interrupt input and the
designated signal edge is detected
(n = 1, 0)
[Clearing condition]
When IRRI1 and IRRI0 = 1, they are cleared by writing 0
* Only 0 can be written for flag clearing.
Rev. 7.00 Mar. 08, 2010 Page 80 of 510
REJ09B0024-0700