HD6473847RHV Datasheet, PDF (96/546 Pages) Renesas Technology Corp – Renesas 8-Bit Single-Chip Microcomputer H8 Family / H8/300L Super Low Power Series

Section 2 CPU
Reset state
Reset cleared
Reset occurs
Exception-handling state
Reset
occurs
Reset
occurs
Interrupt
source
occurs
Interrupt
source
occurs
Exception-
handling
complete
Program halt state
Program execution state
SLEEP instruction executed
Figure 2.16 State Transitions
2.9 Usage Notes
2.9.1 Notes on Data Access to Empty Areas
The address space of this LSI includes empty areas in addition to the ROM, RAM, and on-chip
I/O registers areas available to the user. When data is transferred from CPU to empty areas, the
transferred data will be lost. This action may also cause the CPU to malfunction. When data is
transferred from an empty area to CPU, the contents of the data cannot be guaranteed.
2.9.2 Access to Internal I/O Registers
Internal data transfer to or from on-chip peripheral modules other than the on-chip ROM and
RAM areas makes use of an 8-bit data width. If word access is attempted to these areas, the
following results will occur.
Word access from CPU to I/O register area:
Upper byte: Will be written to I/O register.
Lower byte: Transferred data will be lost.
Word access from I/O register to CPU:
Upper byte: Will be written to upper part of CPU register.
Lower byte: Data which is written to lower part of CPU register is not guaranteed.
Rev. 7.00 Mar. 08, 2010 Page 64 of 510
REJ09B0024-0700